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This article presents a dual-band power amplifier for 28 and 39 GHz frequency bands based on a new dual-path transformer (DPT). This DPT can provide two optimum inductive values at two different frequency bands to optimally design the matching networks for each band without using any switch circuitries. It operates as the output and input matching networks in a parallel power combiner and divider, respectively. DPT-based PA breaks the trade-off between bandwidth and performance in conventional wideband PAs by separating one whole wideband into two narrow bands providing optimum input and output matchings for each band. The DPT-based PA has two input and two output ports. One set of input and output ports is dedicated to a lower frequency band and the other set of input and outport ports can be used for a higher frequency band. Each output port can drive a separate antenna in a phased array for each frequency band. The proposed PA prototype is fabricated in a 65 nm CMOS process achieving 15.3 and 14.0 dBm of saturated output power in 28 and 39 GHz. The peak efficiency of the PA is 34.1% and 30.2% at 28 and 39 GHz frequency bands. The PA has a measured EVM with 64-QAM modulated signal in both frequency bands showing −25.03 and −25.10 dB in the low and higher frequency bands, respectively. 

Millimeter-wave (mmWave) systems require a large number of antennas, which makes the beam training challenging and time-consuming for conventional phased arrays. Recently, a true-time-delay (TTD) array-based beam training algorithm has been shown as an effective solution to overcome the training overhead in large arrays. In this paper, we present a custombuilt over-the-air (OTA) testbed to study the effects of hardware impairments on the TTD-based beam training and verify its feasibility in a real system. We proposed an orthogonal matching pursuit (OMP) based reconstruction algorithm along with a phase calibration dictionary to combat nonidealities such as strong frequency selectivity and phase misalignment in the received raw IQ signal. Post-processing results showed that with the nonideality effects properly handled, the 3D TTD beam training algorithm can achieve high AOA estimation accuracy. 

This article introduces an innovative four-port dual-path inductor designed to deliver two distinct inductance values to the resonator of a voltage-controlled oscillator (VCO). The switching between the inductor’s two excitation modes, even and odd, is determined by the differential excitation’s input polarity, eliminating the need for a series switch. Thus, the inductor has a high-quality factor ( Q ) in both modes. The inductances in these modes can be independently set based on desired frequencies. This inductance change achieves coarse frequency tuning, while fine-tuning is realized by a conventional 2-bit capacitor bank with a small-size varactor. This inductor is well suited for designing multiband VCOs aimed at widely spaced operation frequency bands. Apart from the inductance change, a particular case of mode-switching capacitor is employed to extend to another frequency band in between the low and middle bands, achieving triple-band oscillation. As a result, this article presents two VCOs designed using the proposed inductor: one in class-D biasing in a 65-nm CMOS process and another with class-B biasing in a 180-nm BiCMOS process. Both VCOs successfully oscillate across three distinct frequency bands, centered at 19, 28, and 36 GHz, while maintaining outstanding phase noise and minimal power consumption. Measurement results show good match with simulation, resulting in a peak figure of merit (FoM) of 185.7 dBc/Hz at 18.5 GHz, and occupy 0.088- mm2 (250 × 350 μ m) area in both processes. 

With the increasing complexity of highly integrated system on chips (SoCs), the power management system (PMS) is required to provide several power supplies efficiently for individual blocks. This paper presents a single-inductor multiple outputs (SIMO) an inductor-first hybrid converter that generates three outputs between 0.4V and 1.6V from a 1.8V input. The proposed multiple-output hybrid power stage can improve the conversion efficiency by reducing inductor current while extending the output voltage range compared with the existing hybrid topologies. In addition, the proposed converter employs an on-chip switched-capacitor power stage (SCPS) with a dual switching frequency technique, resulting in a fast response time, low cross-regulation, and reduced number of on-chip pads. Measurement results show that the converter achieves a peak efficiency of 87.5% with a maximum output current of 450mA. The converter is integrated with a fast voltage regulation loop with a 500MHz system clock to achieve less than 0.01mA/mV cross-regulation and a maximum 20mV overshoot at full-load transient response. The design is fabricated in the standard 180nm CMOS technology